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Merging resistive switches and CMOS for functional circuits

The focus of research of the former Chair of Electrical Engineering and Computer Systems (EECS) at RWTH Aachen University was given in the field of circuits based on resistive switches (RS) and nano-scaled CMOS devices. Particular application domains cover nonvolatile distributed memories, reconfigurable logic, and artificial neural networks

The focus of research of the former Chair of Electrical Engineering and Computer Systems (EECS) at RWTH Aachen University was given in the field of circuits based on resistive switches (RS) and nano-scaled CMOS devices. Particular application domains cover nonvolatile distributed memories, reconfigurable logic, and artificial neural networks. One of the most striking challenges in the design of such circuits is to tackle the significant impact of variability on circuit reliability, notably in consideration of reduced signal energies, speed requirements, and demands for minimal area occupation. In contrast to standard methods, focusing on functional aspects of systems a-priori, concerns about reliability were seen as a premise here while the realization of a particular function gets constrained by reliability demands. In order to develop effective means to preserve robustness against various physical sources of perturbations, the research program is based on three pillars: (i) Preparation of realistic models of devices (RS, CMOS) and interconnect as well for circuit simulation. At this, typical influence factors are even by static parameter variability caused by process variability, random telegraph noise and electronic traps, random movement of charged ions, and cross-coupling of signals by electromagnetic fields. (ii) Identification of suitable functional circuits which could replace the gates used in standard CMOS technology. A particular focus was set on circuit concepts which allow for a significant increase in the gate fan-in (associative mapping of operands). Here, the degree of parallelism could be increased while the speed of individual gates could be lowered to meet particular reliability demands. In doing so, extensive Monte-Carlo simulations of fundamental circuits were carried out to characterize their performance in regard to power consumption, bit error rate, and speed. (iii) Identification of elementary passive and active measures to enhance the systems robustness dependent on the considered level (device, circuit, architecture, system). Concepts were evaluated which include feedback loops, non-volatile circuit calibration and adaptation as well as the use of particular error detecting codes.

References:

A. Heittmann, T.G. Noll, Variability of Multilevel Switching in Scaled Hybrid RS/CMOS Nanoelectronic Circuits: Theory, The European Physical Journal Applied Physics, 63, 14404, 2013 doi: 10.1051/epjap/2013120482


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